The present invention relates to a semiconductor memory device with field effect transistors.
Recently, the degree of integration of integrated circuits has been rapidly improved. Particularly, in semiconductor memories, the degree of integration has been increased by two times every year and, in the near future, a semiconductor memory of several megabits per chip will be realized. In realizing such a semiconductor memory with a high degree of integration, it is essential to develop a precise manufacturing technique to effectively use dynamic memory cells each formed of one transistor and one capacitor and to precisely set the distance between the source and the drain of the transistor to be 1.mu., for example. The miniaturization of the transistor to form a dynamic memory cell necessitates the lowering of a power source voltage used. With the lowering of the power source voltage used, the amount of charge stored representing data to be written into a memory cell decreases so that the value of a signal voltage also decreases. It is very difficult to design a sense amplifier capable of reliably sensing such a low voltage which also permits sufficiently long refresh intervals.
FIG. 1 shows a basic circuit of a conventional dynamic memory including a memory cell formed of a single transistor and a single capacitor. In FIG. 1, a field effect transistor (FET) Q1 and a capacitor C1 cooperate to form a memory cell and a field effect transistor Q0 and a capacitor CO cooperate to form a dummy cell. The FET's Q0 and Q1 are connected at their gates to word lines WL1 and WL2, respectively. These word lines WL1 and WL2 are connected to receive clock pulses .phi. through current paths of FET's Q2 and Q3, respectively, which receive at their drains clock pulses generated from a decoder circuit (not shown). The drains of the transistors Q0 and Q1 are respectively connected to corresponding terminals of a sense/refresh amplifier SA, through digit lines DL0 and DL1. These digit lines DL0 and DL1 are parasitically connected with stray capacities C2 and C3, respectively. These digital lines DL0 and DL1 are further connected to power source terminals V.sub.DD through current paths of FET's Q4 and Q5, respectively.
In FIG. 1, when the word line WL2 is energized by a clock pulse supplied from a word line selection circuit (not shown) through the FET Q3, the dummy cell applies a reference voltage to the sense/refresh amplifier SA through the digit line DL1. The sense/refresh amplifier SA supplies to an output circuit (not shown) an output signal corresponding to a difference between a signal voltage and a reference voltage coming from the memory cell and the dummy cell by way of the digit lines DL0 and DL1, respectively.
Assume now that data is loaded into the memory cell with a voltage Vw and, after a given time lapses, the word lines WL1 and WL2 are energized for reading out the data stored in the memory cell. At this time, the signal voltage Vs at each terminal of the sense/refresh amplifier SA is given ##EQU1## where V.sub.DROP is the amount by which the data voltage is attenuated within the memory cell during a time period from the write of data to the read of data.
The data voltage Vw loaded into the memory cell is lower than the power source voltage V.sub.DD by the threshold voltage V.sub.TH of the FET Q1. This is for the following reason. In the circuit shown in FIG. 1, for example, the digit line DL0 is held at most at the potential of V.sub.DD and the word line WL1 is held at the maximum voltage of V.sub.DD when it is energized. In other words, when the digit line DL0 and the word line WL1 are kept at the potential of V.sub.DD, the field effect transistor Q1 operates in a pentode mode so that the charged voltage across the capacitor C1 is suppressed below (V.sub.DD -V.sub.TH).
When 12 V, for example, is used for the power source voltage, the write voltage is approximately 10 V. In a very large scale integrated memory device, the distance between the source and drain of the field effect transistor forming each memory cell is chosen to be 1 to 2.mu., for example, and the power source voltage V.sub.DD is set to a low voltage, for example, 2 to 5 V. In this case, in order to reliably operate the field effect transistor, the threshold voltage V.sub.TH of the FET must be set to be 0.4 to 0.5 V or more. Accordingly, in order to write data into the memory cell in the above-mentioned manner, the utilization efficiency of the power source voltage is poor so that the write voltage is very low. This leads to the narrowing of the design and operation margins of the memory cell.